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publication# 080160 rev : d amendment: /0 issue date: april 2000 am79213/AM79C203/031 advanced subscriber line interface circuit (aslic?) device advanced subscriber line audio-processing circuit (aslac?) device distinctive characteristics performs all of the functions of a codec-filter single channel architecture performs battery-feed, ring-trip, signaling, coding, hybrid and test (borscht) functions single hardware design meets multiple country requirements through software programming standard microprocessor interface industry standard pcm interface with full-time slot assignment monitor of two-wire interface voltage and current for subscriber line diagnostics low idle power per line on-hook transmission only battery and +5 v supplies needed exceeds lssgr and ccitt central office requirements off-hook and ground-key detectors with programmable thresholds programmable line feed characteristics independent of battery voltage built-in voice path test modes analog and digital hybrid balance capability adaptive hybrid balance capability linear power feed with power management and thermal shutdown features abrupt and smooth polarity reversal power-cross detection in ringing and non- ringing states software programmable ? dc loop feed characteristics and current limit ? loop supervision detection thresholds ? off-hook detect debounce interval ? two-wire ac impedance ? transhybrid balance ? transmit and receive gains ? equalization ? digital i/o pins ? a-law/-law selection linear data available on pcm ports for custom compression and expansion compatible with inexpensive protection networks. accommodates low tolerance fuse resistors while maintaining longitudinal balance to bellcore specifications. power/service denial state small physical size integrated ring trip function four relay drivers with built-in energy absorption zener diodes synchronized ring relay operation: zero volts ac on, zero current off software enabled normal or automatic ring-trip state on-chip 12 khz and 16 khz metering generation with on and off meter pulse shaping supports loop-start and ground-start signaling 0c to +70c commercial operation guaranteed by production testing ?40c to +85c temperature range operation available
2 am79213/AM79C203/031 data sheet table of contents distinctive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 linecard block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 aslic device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 aslac device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 connection diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 32-pin plcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 44-pin plcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 aslic device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 aslac device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 aslic/aslac devices functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 electrical requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 absolute maximum electrical and thermal ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 aslic device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 aslac device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 environmental . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 performance specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 aslic device relay driver schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 input and output waveforms for ac tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 master clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 microprocessor interface (input mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 microprocessor interface (output mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 pcm highway timing for xe = 0 (transmit on negative pclk edge) . . . . . . . . . . . . . . . . . 36 pcm highway timing for xe = 1 (transmit on positive pclk edge) . . . . . . . . . . . . . . . . . 37 aslic/aslac devices linecard schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 programmable filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 general description of csd coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 physical dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 pl032 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 pl044 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 revision summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
aslic/aslac products 3 list of figures figure 1. transmit and receive path attenuation vs. frequency . . . . . . . . . . . . . . . . . . . 26 figure 2. group delay distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 3. a-law gain linearity with tone input (both paths) . . . . . . . . . . . . . . . . . . . . . . . 28 figure 4. -law gain linearity with tone input (both paths) . . . . . . . . . . . . . . . . . . . . . . . 28 figure 5. total distortion with tone input (both paths) . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 6. a/a overload compression. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 7. aslic/aslac typical linecard schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 list of tables table 1. power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 2. aslic device dc specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 3. aslic device relay driver specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 4. aslic device transmission specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 5. aslac device dc specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 6. aslac device transmission and signaling specifications . . . . . . . . . . . . . . . . 22 table 7. microprocessor interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 8. pcm interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 9. master clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 10. user-programmable components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 11. aslic/aslac devices linecard parts list . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4 am79213/AM79C203/031 data sheet the am79213/AM79C203/031 advanced subscriber line interface chip set implements a universal telephone line interface function. this enables the design of a single, low cost, high performance, fully software programmable line interface card for multiple country applications world wide. all ac, dc, and signaling parameters are fully programmable via the microprocessor interface. additionally, the aslic device and aslac device have integrated self test and line test capabilities to resolve faults to the line or line circuit. the integrated test capability is crucial for remote applications where dedicated test hardware is not cost effective. the technical reference, pid 21325a is recommended to be used with this document. linecard block diagram tr a n s m i t receive dc feed control metering loop voltage monitor loop current monitor aslic device operat- ing state relay driver inputs ad bd sa sb loop voltage sense resistors a(tip) b(ring) ringer supply ring-feed resistor relay driver outputs aslac device ringing-current sense resistors rfa pcm aslic device rfb mpi mpi and pcm backplane ring and te s t relays
aslic/aslac products 5 ordering information aslic device must order AM79C203 or AM79C2031 with the device below. am79213 j c temperature range c = commercial (0 c to 70 c)* package type j = 32-pin plastic leaded chip carrier (pl 032) device number/description am79213 advanced subscriber line interface circuit valid combinations valid combinations list configurations planned to be supported in volume for this device. consult the local legerity sales office to confirm availabil- ity of specific valid combinations and to check on newly released combinations. valid combinations am79213 jc note: * functionality of the device from 0c to +70c is guaranteed by production testing. performance from ?40c to +85c is guaranteed by characterization and periodic sampling of production units.
6 am79213/AM79C203/031 data sheet ordering information (continued) aslac device must order am79213 with the device below. AM79C203/031 j c temperature range c = commercial (0 c to 70 c)* package type j = 32-pin plastic leaded chip carrier (pl032) AM79C203 only j = 44-pin plastic leaded chip carrier (pl044) AM79C2031 only device number/description AM79C203/031 advanced subscriber line audio-processing circuit valid combinations valid combinations list configurations planned to be supported in volume for this device. consult the local legerity sales office to confirm availabil- ity of specific valid combinations and to check on newly released combinations. valid combinations AM79C203 jc AM79C2031 note: * functionality of the device from 0 c to +70 c is guaranteed by production testing. performance from ? 40 c to +85 c is guaranteed by characterization and periodic sampling of production units.
aslic/aslac products 7 connection diagrams top view 32-pin plcc hpb hpa bal1 vtx vref ringout ry2out tmg c5 c4 c2 c3 am79213 1 2 3 4323130 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 sa ry3out nc idc rsvd qbat c1 vdc vlbias idif isum gnd rsn ry1out vcc vbat bgnd bd ad sb 1 2 3 4323130 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 AM79C203 vccd i/o1 vcca idc vlbias iref iab isum idif irta irtb fs dclk di/o cs c2 c1 i/o2 int vm vout vref agnd vin rst dxa tcsa dgnd pclk dra mclk ibat notes: 1. rsvd = reserved. do not connect to this pin. 2. nc = no connect
8 am79213/AM79C203/031 data sheet connection diagrams (continued) top view 44-pin plcc 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 7 8 9 10 11 12 13 14 15 16 17 1 2 3 4 540 41 42 43 644 AM79C2031 vcca vccd dclk c1 c2 i/o1 fs idc vlbias ibat iab isum idif irta irtb i/o3 i/o4 cs di/o i/o2 rsvd iref rsvd int rsvd vm vout vref agnd vin rsvd rst rsvd rsvd dxa dxb tsca dgnd pclk dra drb tcsb mclk rsvd note: rsvd = reserved. do not connect to this pin.
aslic/aslac products 9 pin descriptions aslic device pin names type description ad, bd output a and b line drivers. these pins provide the currents to the a and b leads of the sub- scriber loop. bal1 input pre-balance. this pin receives voltages that are added to the vtx output signal. they can be used to cancel out the metering echo in the transmit path. bgnd gnd battery ground. this pin connects to the ground return for central office or talk battery. c2 ? c1 input aslic device control. these ternary logic input pins control the operating state of the aslic device. c5 ? c3 input test relay control. these are control inputs for the test relay drivers in the aslic device. a logic low turns on the relay driver and activates the relay. c3 controls ry1out, c4 controls ry2out, and c5 controls ry3out. gnd gnd analog and digital ground return for vcc. hpa, hpb capacitor high-pass filter capacitor connections. these pins connect to chp, the external high- pass filter capacitor that isolates the dc control loop from the voice transmission path. idc input dc loop control current. the dc loop current control line from the aslac device is con- nected to this pin. an internal resistance is provided between the idc pin and rsn. an external noise filter capacitor should be connected between this pin and vref. idif output a ? b leg current. the current at this pin is proportional to the difference of the currents flowing out of the ad pin and into the bd pin of the aslic device. isum output a + b leg current. the current at this pin is proportional to the absolute value of the sum of the currents flowing out of the ad pin and into the bd pin of the aslic device. qbat power quiet battery voltage. the qbat pin is connected to the substrate. ringout, ry1out, ry2out, ry3out output relay drivers. these are open collector, high current relay driver outputs with emitters internally connected to bgnd. to absorb the inductive pulse from the relay coils, an in- ternal zener diode is connected between the collector of each driver and bgnd. rsn input receive summing node. the metallic current (both ac and dc) between ad and bd is equal to aslic device current gain, k1, times the current into this pin. networks that pro- gram receive gain and two-wire impedance connect to this node. this input is nominally at vref potential. rsvd input reserved. this is used during legerity testing. in the application, this pin must be floating. sa, sb input a and b lead voltage sense. these pins sense the voltages on the line side of the fuse resistors at the a and b leads. external sense resistors, rsa and rsb, are required to protect these pins from lightning or power cross conditions. tmg thermal thermal management. a resistor connected from this pin to vbat reduces the on-chip power dissipation by absorbing excess power from the aslic device for short-loop con- ditions. vbat power battery voltage. this pin supplies battery voltage to the line drivers. vcc power power supply. this is the positive supply for low voltage analog and digital circuits in the aslic device. vdc output dc loop voltagethe voltage on this output is referenced to vref and is proportional to the negative absolute value of the dc subscriber loop voltage between a and b. this volt- age is a fraction ( ) of the voltage between hpa and hpb. this pin connects to the iab pin on the aslac device through external resistor rab. a voltage that is significantly more positive than vref on the vdc pin indicates that the aslic device is in thermal shutdown.
10 am79213/AM79C203/031 data sheet aslac device vlbias input longitudinal offset voltage. the input to this pin is the offset reference voltage for the aslic device longitudinal control loop. vref input analog reference. this voltage is provided by the aslac device and is used by the aslic device for internal reference purposes. all analog input and output signals inter- facing to the aslac device are referenced to this pin. nominally set to 2.1 v. vtx output four-wire transmit signal. the voltage between this pin and vref is a scaled version of the ac component of the voltage sensed between the sa and sb pins. one end of the two-wire input impedance programming network connects to vtx. the voltage at vtx swings positive and negative about vref. pin names type description agnd gnd analog (quiet) ground. vref is referenced to this ground. c2 ? c1 output aslic device control. these ternary logic output pins are dedicated to controlling the op- erating state of the aslic device. the levels of these outputs are logic high, logic low, and high impedance. cs input, active low chip select. the chip select input (active low) enables the device so commands and data can be written to or read from it. if chip select is held low for 16 or more dclk cy- cles (independent of mclk or pclk), a hardware reset is executed at the time chip se- lect returns to logic 1. dclk input data clock. the data clock input shifts data into or out of the microprocessor interface of the aslac device. the maximum clock rate is 4.096 mhz. dgnd gnd digital ground. digital ground return. di/o input/output data input/output. control data is serially written into and read out of the aslac device via the di/o pin, with the most significant bit first. the data clock (dclk) determines the data rate. di/o is high impedance except when data is being transmitted from the aslac device under control of cs . dra, drb input receive pcm data. receive pcm data is received serially on either the dra or drb port, with port selection under user program control. data is received, most significant bit first, in 8-bit pcm or 16-bit linear 2 ? s complement bursts every 125 s at the pclk rate. the receive port is unaffected by the setting of the smode bit. (drb ? 44-pin plcc only.) dxa, dxb output transmit pcm data. transmit pcm data is transmitted serially through either the dxa or dxb port, with port selection under user control. the transmission data output is available every 125 s and is shifted out, most significant bit first, in 8-bit pcm or 16-bit linear 2 ? s complement bursts at the pclk rate. dxa/b are high impedance between bursts and while the device is in the inactive state. for signaling register operation on the pcm highway, see the smode description. (dxb ? 44-pin plcc only.) fs input frame sync. the frame sync signal is an 8 khz pulse that identifies the beginning of a frame. the aslac device references individual time slots with respect to this input, which must be synchronized to pclk. iab input loop voltage sense. the iab pin is a current summing node referenced to vref. an ex- ternal resistor (rab) is connected between this pin and the vdc pin of the aslic device, in normal operation, current flows out of this pin. when the aslic device is in thermal shutdown, current will be forced into this pin. ibat input battery voltage sense. the ibat pin is a current summing node referenced to agnd and receives a current that is proportional to the system battery voltage. a sense resistor/ca- pacitor network is connected between the qbat pin of the aslic device and the ibat pin. pin names type description
aslic/aslac products 11 idc output dc loop control current. the idc output supplies a current to the aslic device for pro- portional control of the dc loop current flowing through the subscriber loop. idif input longitudinal sense. idif is a current input pin fed by the idif pin of the aslic device. the current in this pin is used by the aslac device for supervisory and diagnostic func- tions. the idif pin has an internal input resistance so an external longitudinal noise filter capacitor can be connected. int output, active low interrupt. a logic 0 on this pin indicates one or more of the bits in the signaling register has changed states. an interrupt will be generated when activity is sensed on any signal in the signaling register not masked by the mask register. once an unmasked activity is sensed, the int output will be driven low and held at that state until cleared. see the description of configuration register 6 for operation. i/o 1 , i/o 2 , i/o 3 , i/o 4 input/output control ports. these control lines are ttl compatible and each can be programmed as an input or an output. when programmed as inputs, they can monitor external, ttl com- patible logic circuits. when programmed as outputs, they can control an external logic de- vice or they can be connected to pin c3, c4, or c5 of the aslic device to control test relay drivers ry1out, ry2out and ry3out (i/o 3 , i/o 4 , 44-pin plcc version only). in the output mode, these pins are controlled by the i/o 1 , i/o 2 , i/o 3 , and i/o 4 bits in the channel control register, mpi command 17. iref reference current reference. an external resistor (rref) connected between this pin and analog ground generates an accurate on-chip reference current. this current is used by the aslac device in its dc feed and loop-supervision circuits. irta, irtb inputs ring trip sense. these pins are current summing nodes referenced to vref. they pro- vide terminations for external resistors rsr1 and rsr2, which sense the voltages on both sides of the ringing feed resistor connected to the ring bus. to determine the ring- ing current in the loop, the aslac device senses the difference between the currents in these pins. isum input metallic sense. isum is a current input pin and is fed by the isum pin of the aslic de- vice. the absolute value of the current in this pin is used by the aslac device for super- visory and diagnostic functions. mclk input master clock. the master clock is used to operate the digital signal processor. mclk can be 2.048 mhz, 4.096 mhz or 8.192 mhz. mclk may be asynchronous to pclk. upon initialization, the mclk input is disabled and relevant circuitry is driven by a connection to pclk. the mclk connection may be reestablished under user control. pclk input pcm clock. the pcm clock determines the rate at which pcm data is serially shifted into or out of the pcm ports. pclk is an integer multiple of the frame sync frequency. the maximum clock frequency is 8.192 mhz and the minimum clock frequency is 128 khz for companded data. the minimum clock frequency for linear or companded data plus sig- naling data is 256 khz. the pclk clock may be asynchronous to mclk if the initial con- nection state is disabled under user control. rst input, active low reset. a logic 0 on this pin resets the aslac device to initial default conditions. it is equivalent to a hardware reset command. a signal less than 100 ns should not cause a reset. to ensure proper reset, the minimum length of a reset pulse is 50 s. tsca , tscb open drain outputs time slot control. the time slot control outputs are open drain (requiring an external pull-up resistor to vccd) and are normally inactive (high impedance). tsca is active (low) when pcm data is present on dxa, and tscb is active (low) when pcm data is present on dxb. (tscb and drb ? 44-pin plcc only.) vcca power analog power supply. vcca is internally connected to substrate near the analog i/o section. vccd power digital power supply. vccd is internally connected to substrate near the digital section. vin input analog input. the analog output (vtx) from the aslic device is applied to the aslac device transmit path input, vin. the signal is sampled, processed, encoded, and trans- mitted on the pcm highway. pin names type description
12 am79213/AM79C203/031 data sheet vlbias output longitudinal reference. vlbias is programmed by voff and supplies the longitudinal reference voltage for the longitudinal control loop to the aslic device. vm output 12/16 khz metering signal. for 12/16 khz teletax, an internally generated and shaped 12 or 16 khz sine wave metering pulse is output from this pin. vout output analog output. the voice data from the received pcm channel (timeslot) is digitally pro- cessed and converted to an analog signal which is present on the vout pin of the aslac device. vref output analog reference. this pin provides a voltage reference to be used as the analog zero level reference on the aslic device. pin names type description
aslic/aslac products 13 aslic/aslac devices functional description the aslic/aslac devices chip set integrates all func- tions of the subscriber line. the chip set comprises an aslic device and an aslac device. the set provides two basic functions: 1) the aslic device, a high-voltage, bipolar device that drives the subscriber line, maintains longitudinal balance, and senses line conditions; and 2) the aslac device, a low-voltage cmos device that combines codec, dc feed control, and line supervi- sion. a complete schematic of a linecard using the aslic/aslac devices chip set is shown in the figure 7. the aslic device uses reliable, bipolar technology to provide the power necessary to drive a wide variety of subscriber lines. it can be programmed by the aslac device to operate in eight different states that control power consumption and signaling states. this enables full control over the subscriber loop. the aslic device is customized to be used exclusively with the aslac device, providing a two-chip universal line interface. the aslic device requires only a +5 v power supply and a negative battery supply for its operation. the aslic device implements a linear loop current feeding method with the enhancement of thermal man- agement to limit the amount of power dissipated on the aslic device by dissipating excess power in an external resistor. the aslac device is a high-performance, cmos co- dec/filter device with additional digital filters and cir- cuits that allow software control of transmission, dc feed, and supervision. advanced cmos technology makes the aslac device an economical device that has both the functionality and the low power consumption required by linecard design- ers to maximize linecard density at minimum cost. when used with an aslic device, the aslac device provides a complete software-configurable solution to linecard functions. in addition, the aslic/aslac devic- es chip set provides system-level solutions for loop su- pervisory functions and metering. in total, the aslic/ aslac devices chip set provides a programmable so- lution that can satisfy worldwide linecard requirements by software configuration. all software-programmed coefficients and dc feed pa- rameters are easily calculated with the amslac3 soft- ware. this software is provided free of charge and runs on an ibm-compatible pc. it allows the designer to enter a description of system requirements, then the software returns the necessary coefficients and the predicted system response. the aslac device uses the industry standard micro- processor (mpi) and pcm interfaces to communicate with the system and for interfacing to the 64 kilobit per second voice network. the aslic device interface unit inside the aslac device processes information regarding line voltages, loop cur- rents, and battery voltage levels. these inputs allow the aslac device to place several key aslic device perfor- mance parameters under programmable supervision. the main functions that can be observed and/or controlled through the aslac device control interface are: dc feed characteristics ground-key detection off-hook detection metering signal longitudinal operating point subscriber line voltage and currents ring trip abrupt and smooth battery polarity reversal to accomplish these functions, the aslac device col- lects the following information from the aslic device and the central office system: the sum and difference of the currents in each loop leg, isum, and idif currents proportional to the: ? voltage across the loop (iab) ? battery voltage (ibat) ? ringing current in the loop (irta ? irtb) the outputs supplied by the aslac device are then: a current proportional to the desired dc loop cur- rent (idc) a voltage proportional to the desired longitudinal off- set voltage (vlbias) a 12/16 khz metering signal (appears on vm for 12/16 khz teletax) the aslac device performs the codec and filter func- tions associated with the four-wire section of the sub- scriber line circuitry in a digital switch. these functions involve converting an analog voice signal into digital pcm samples and converting digital pcm samples back into an analog signal. during conversion, digital filters are used to band-limit the voice signals. the user-programmable filters set the receive and transmit gain, perform the transhybrid balancing func- tion, permit adjustment of the two-wire termination im- pedance, and provide frequency response adjustment (equalization) of the receive and transmit paths. adap- tive transhybrid balancing is also included.
14 am79213/AM79C203/031 data sheet the pcm data can be either 8-bit companded a-law code, 8-bit companded -law code, or 16-bit linear code. voice data is transmitted and received via the pcm highway; control information is written to and read from the aslac/aslic devices chip set over the mi- croprocessor interface. besides the codec functions, the aslac device pro- vides all the sensing, feedback, and clocking neces- sary to completely control aslic device functions with programmable parameters. the line status is continu- ously available in the aslac device signaling regis- ter, which is continuously available via the mpi interface, or on the pcm highway via a user-program- mable mode. a programmable interrupt provides add- ed flexibility in monitoring line status. system-level parameters under programmable control include ac- tive and disable loop-current limits, feed resistance, and apparent battery-feed voltage. the longitudinal operating point is programmable to optimize the aslic device signal swing capability. the aslac device provides signals at 12 or 16 khz for metering functions. the frequency and level of these signals are programmable. the aslac device provides extensive loop supervision capability, including off-hook, ring-trip, and ground-key detection. detection thresholds for these functions are programmable. a programmable debounce timer is available that eliminates false detection due to contact bounce. for subscriber line diagnostics, ac and dc line conditions can be monitored using special test modes. results are read using the mpi commands.
aslic/aslac products 15 electrical requirements power dissipation loop resistance = 0 to (not including fuse resistors), 2 x 50 ? fuse resistors, vbat = qbat = ? 48 v, vcc = +5 v. for power dissipation measurements, dc feed conditions are programmed as follows: vapp (apparent voltage) = 50.2 v ila (active state current limit) = 42.3 ma ild (disable state current limit) = 21.2 ma rfd (feed resistance) = 807 ? vas (anti-sat activate voltage) = 8.2 v n2 (anti-sat feed resistance factor) = 2 voff (longitudinal offset voltage) = 6 v rtmg (thermal management resistor) = 1200 ? rref (reference current setting resistor) = 7.87 k ? thermal resistance the junction-to-air thermal resistance of the aslic de- vice in a 32-pin plcc package will be less than 45 c/w. the junction-to-air thermal resistance of the aslac de- vice in a 32-pin plcc package will be less than 45 c/w. the junction-to-air thermal resistance of the aslac de- vice in a 44-pin plcc package will be less than 44 c/w. table 1. power dissipation description test conditions min typ max unit aslic device power dissipation normal polarity on-hook disconnect 30 70 mw on-hook standby 50 105 on-hook disable 120 215 on-hook active 330 450 off-hook active r l = 294 ? 850 1200 off-hook disable r l = 600 ? 800 950 aslac device power dissipation mclk, pclk = 2.048 mhz aslac device activated 85 110 aslac device inactive, mpi standby state command issued 22 25 aslac device power dissipation mclk, pclk > 2.048 mhz aslac device activated 95 120 aslac device inactive, mpi standby state command issued 23 26
16 am79213/AM79C203/031 data sheet absolute maximum electrical and thermal ratings aslic device storage temperature................... ? 55 c t a +150 c ambient temperature, under bias................................ ? 40 c t a +85 c ambient relative humidity (noncondensing).................................. 5% to 100% v cc with respect to agnd/dgnd......... ? 0.4 v to +7 v v bat , q bat with respect to bgnd....... +0.4 v to ? 75 v v cc with respect to v bat , q bat ......................... +80 v bgnd with respect to agnd/dgnd ................................ ? 0.5 v to +0.5 v voltage on relay outputs....................................... +7 v ad or bd to bgnd: continuous ........................................ ? 75 v to +1 v 10 ms (f = 0.1 hz).............................. ? 75 v to +5 v 1 s (f = 0.1 hz)............................... ? 90 v to +10 v 250 ns (f = 0.1 hz)......................... ? 120 v to +15 v current into sa or sb: 10 s rise to ipeak; 1000 s fall to 0.5 ipeak; 2000 s fall to i = 0.......................... ipeak = 5 ma current into sa or sb: 2 s rise to ipeak; 10 s fall to 0.5 ipeak; 20 s fall to i = 0 ......................... ipeak = 12.5 ma current through ad or bd ............................. 150 ma c5 ? c1 to dgnd or agnd ............... ? 0.4 v to v cc + 0.4 v maximum power dissipation, t a = 70 c ........... 1.67 w note: thermal limiting circuitry on chip will shut down the cir- cuit at a junction temperature of about 160 c. the device should never be exposed to this temperature. operation above 145 c junction temperature may degrade device reli- ability. see the slic packaging considerations for more in- formation. aslac device storage temperature .................. ? 60 c t a +125 c ambient temperature, under bias ............................... ? 40 c t a +85 c ambient relative humidity (noncondensing) .................................. 5% to 100% v cca , v ccd with respect to dgnd ....... ? 0.4 v to +6 v v cca with respect to v ccd .................................0.4 v v in with respect to dgnd ........ ? 0.4 v to v cca + 0.4 v agnd..................................................... dgnd 0.4 v latch up immunity (any pin)...........................100 ma any other pin with respect to dgnd ............................... ? 0.4 v to v cc + 0.4 v stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum rat- ings for extended periods may affect device reliability. operating ranges environmental ambient temperature .........0 c to +70 c commercial* ambient relative humidity.......................... 15% to 85% aslic device v cc ..............................................................+5 v 5% v bat , q bat ............................................ ? 18 v to ? 70 v bgnd with respect to gnd ....... ? 100 mv to +100 mv load resistance on v tx to ground ............... 10 k ? min aslac device supplies v cca , v ccd ...................................+5 v 5% dgnd ..................................................................... 0 v agnd.................................................. dgnd 50 mv operating ranges define those limits over which the function- ality of the device is guaranteed by production testing. * functionality of the device from 0 c to +70 c is guaranteed by production testing. performance from ? 40 c to +85 c is guaranteed by characterization and periodic sampling of pro- duction units.
aslic/aslac products 17 performance specifications (see note 1) t a = 0 c to 70 c unless otherwise noted. table 2. aslic device dc specifications no. item condition min typ max unit note 1 2-wire loop voltage standby state, r l = 1 m ? q bat ? 1.8 q bat ? 1.1 q bat ? 0.5 v 4 active state, rl ad ? bd = 600 ? irsn = 140 a 19.51 21.1 22.68 disable state, rl ad ? bd = 600 ? irsn = 80 a 11.34 12.19 13.04 2 feed resistance per leg at pins ad and bd standby state 130 250 375 ? 3 isum current standby state, r l = 1930 ? 44.6 56 a idif current standby state a to q bat b to ground 35.4 43.4 4 ternary input voltage boundaries for c2 ? c1 pins. mid- level input source must be high impedance or 3-state low boundary 0.8 v high boundary v cc ? 1 logic inputs c2 ? c1 input high current ? 80 200 a input low current 90 200 3-state voltage i c1 = i c2 = 1 a 0.8 3.5 v 4 5 logic inputs c5 ? c3 input high voltage 2.0 input low voltage 0.8 input high current ? 200 40 a input low current ? 400 40 6 v tx output offset bal1 pin open ? 50 +50 mv 7v ref input voltage iref = 1 ma 2.0 2.1 2.2 v 8 , ratio of v dc to loop voltage: tj < 145 c, v dc is referenced to v ref , 35.7 k ? resistor con- nected from v dc to v ref . vsa ? vsb = 40 v. 0.0253 0.0242 0.0232 v/v 9 thermal shutdown threshold voltage output on v dc i vdc = 20 a 4.2 v cc ? 0.4 v 4 10 gain from vlbias pin to ad or bd pin 5.58 6.0 6.42 v/v 11 input resistance to agnd, vlbias pin vlbias = 3 v 20 33.3 k ? vdc vref ? vsa vsb ? ------------------------------------ =
18 am79213/AM79C203/031 data sheet aslic device relay driver schematic no. item condition min typ max unit note 12 isum/iloop iloop = 10 ma 1/333 1/300 1/273 13 idif/ilong ilong = 10 ma 1/667 1/600 1/546 14 input current, sa and sb pins 13 a 4 15 input current hpa and hpb pins 0.1 3 16 idc input impedance 1.26 1.8 3 k ? 17 k1 incremental dc current gain 254 a/a 13 18 metallic offset current 0 ? 0.4 ma table 3. aslic device relay driver specifications item condition min typ max unit note on voltage 25 ma per relay sink 1 relay on 0.225 0.3 v 4 relays on 0.4 0.5 4 40 ma per relay sink 1 relay on 0.45 0.7 4 relays on 0.8 1.0 4 off leakage, each relay driver v oh = +6 v 0 100 a table 4. aslic device transmission specifications no. item condition min typ max unit note 1r sn input impedance f = 300 hz to 3400 hz 1 ? 4 2v tx output impedance 3 3 gain, bal1 to v tx 1.4 1.5 1.6 v/v 4 bal1 input impedance 3.17 5 7.5 k ? 4 5 input impedance a or b to gnd 70 135 ? table 2. aslic device dc specifications (continued) ringout ry1out ry2out ry3out bgnd
aslic/aslac products 19 no. item condition min typ max unit note 6 2- to 4-wire gain ? 10 dbm, 1 khz t a = ? 40 c to 0 c/70 c to 85 c ? 12.19 ? 12.24 ? 12.04 ? 11.89 ? 11.84 db 7 2- to 4-wire gain variation with frequency 300 to 3400 hz relative to 1 khz t a = ? 40 c to 0 c/70 c to 85 c ? 0.1 ? 0.15 +0.1 +0.15 8 2- to 4-wire gain tracking +3 dbm to ? 55 dbm reference: ? 10 dbm t a = ? 40 c to 0 c/70 c to 85 c ? 0.1 ? 0.15 +0.1 +0.15 9 4- to 2-wire gain ? 10 dbm, 1 khz t a = ? 40 c to 0 c/70 c to 85 c ? 0.15 ? 0.20 0+0.15 +0.20 10 4- to 2-wire gain variation with frequency 300 to 3400 hz relative to 1 khz t a = ? 40 c to 0 c/70 c to 85 c ? 0.1 ? 0.15 +0.1 +0.15 11 4- to 2-wire gain tracking +3 dbm to ? 55 dbm reference: ? 10 dbm ? 0.1 ? 0.15 +0.1 +0.15 12 total harmonic distortion 2-wire 300 hz to 3400 hz 0 dbm +4 dbm ? 50 ? 40 4-wire ? 12 dbm ? 8 dbm ? 50 ? 40 2-wire metering overload level vlbias = 2.4 v, iloop = 30 ma, v bat = q bat = ? 60 v, dc load = 200 ? , load at 16 khz = 10 k ? 42 vp-p 4 13 idle channel noise c-message weighted active and disable states 2-wire t a = ? 40 c to 0 c/70 c to 85 c +7 +11 +15 dbrnc 4 4-wire ? 54 psophometric weighted 2-wire t a = ? 40 c to 0 c/70 c to 85 c ? 83 ? 79 ? 75 dbmp 4-wire ? 95 4 14 longitudinal balance (ieee method) normal polarity l - t 200 to 1000 hz t a = ? 40 c to 0 c/70 c to 85 c 1000 to 3400 hz t a = ? 40 c to 0 c/70 c to 85 c 58 53 53 48 63 58 db t - l 200 to 3400 hz 40 l - t, il = 0 50 to 3400 hz 63 4 reverse polarity l - t 200 to 1000 hz t a = ? 40 c to 0 c/70 c to 85 c 50 48 15 psrr (v bat , q bat ) 50 to 3400 hz 25 45 3, 5 3.4 khz to 50 khz 25 40 4 aslic device in anti-sat state (loop open) f = 50 hz, cb = 100 nf f = 200 to 3400 hz, cb = 100 nf 2 12 4, 8 table 4. aslic device transmission specifications (continued)
20 am79213/AM79C203/031 data sheet no. item condition min typ max unit note 16 psrr (v cc ) 50 to 3400 hz 25 45 db 3, 5 3.4 khz to 50 khz 25 35 2, 4 17 low frequency induction (rea method) active state, vlong = 30 vrms, i l = 20 ma, f = 60 hz +23 dbrnc 4 18 longitudinal ac current per wire f = 15 to 60 hz 20 marms table 5. aslac device dc specifications no. item condition min typ max unit note 1 input low voltage (any digital input) ? 0.5 0.8 v 2 input high voltage (any digital input) 2.0 v cc + 0.5 3 input leakage current (any digital input) ? 10 +10 a 15 4 input hysteresis (fs and rst only) 0.5 v 4 5 ternary output voltages c2 ? c1 high voltage i out = 200 a v cc ? 0.85 v low voltage i out = 200 a 0.65 output current mid level ? 1+1a 6 output low voltage on digital outputs dxa, dxb, di/o, tnt , tsca , tscb , i/o 1 , i/o 2 , i/o 3 , i/o 4 i ol = 2 ma 0.4 v tsca , tscb i ol = 14 ma 0.4 i/o 1 , i/o 2 , i/o 3 , i/o 4 i ol = 10 ma 1.0 7 output high voltage (all digital outputs except int in the open drain state and tsc ) i oh = 400 a v cc ? 0.4 8 dc feed ila = 47.6 ma, rfd = 403 ? , n2 = 2, vas = 10.3 v, ibat = 69.9 a 19 idc active state, normal polarity, iab = 0, vapp = 50.2 v 172.7 188.5 204.9 a in resistive-feed region 0.0624 0.0694 0.0764 a/a iab ibat = 69.9 a adjust iab until idc = 0 27.93 29.93 31.93 a19 measured vapp programmed vapp = 50.2 v 2.2 v measured vas programmed vas = 10.3 v 1.6 table 4. aslic device transmission specifications (continued) ? iab ? idc -------------- -
aslic/aslac products 21 no. item condition min typ max unit note 9 idc error among programmed ila, ild any ila or ild programmed value > 20 ma (idc > 78.7 a) 5 % 4, 19 any ila or ild programmed value 20 ma (idc 78.7 a) 4 a19 10 offset voltage allowed on v in ? 50 +50 mv 10 11 v out offset voltage aisn off ? 40 +40 10, 19 aisn on ? 80 +80 10 12 output voltage, v ref load current = 0 to 1 ma source or sink 2.0 2.1 2.2 v 19 13 capacitance load on v ref or v out 200 pf 4 14 output current v out source or sink ? 1+1ma 15 input resistance idif pin to v ref 8.84 13.6 18.36 k ? 6 16 vlbias operating voltage source current < 250 a or sink current < 25 a +1 +2.4 v 18 17 percent error of vlbias voltage for vlbias equation see longitudinal control loop ? 5+5% 18 capacitance load on vlbias 120 pf 6 19 capacitance load on irta or irtb 400 table 5. aslac device dc specifications (continued)
22 am79213/AM79C203/031 data sheet table 6. aslac device transmission and signaling specifications no. item condition min typ max unit note 1 insertion loss a-d d-a a-d + d-a input: 1014 hz, ? 10 dbm0 rg = ar = ax = gr = gx = 0 db, aisn, r, x, b, and z filters disabled t a = 0 c to 70 c t a = ? 40 c to 0 c/70 c to 85 c t a = 0 c to 70 c t a = ? 40 c to 0 c/70 c to 85 c t a = 70 c t a = 0 c ? 70 c; vcc = 4.75 ? 5.25 v t a = ? 40 c to 0 c/70 c to 85 c ? 0.25 ? 0.30 ? 0.25 ? 0.30 ? 0.20 ? 0.25 ? 0.34 0 0 0 0 0 0 0 +0.25 +0.30 +0.25 +0.30 +0.20 +0.25 +0.34 db 7 2 level set error (error be- tween setting and actual value) a-d ax + gx ? 0.1 +0.1 d-a ar + gr ? 0.1 +0.1 3 dr to dx gain in full digital loopback mode dr input: 1014 hz, ? 10 dbm0 rg = ar = ax = gr = gx = 0 db, aisn, r, x, b, and z filters disabled t a = ? 40 c to 0 c/70 c to 85 c ? 0.3 ? 0.35 +0.3 +0.4 4 idle channel noise, psophometric weighted (a-law) ax = 0 db ar = 0 db a-d (pcm output) ? 68 dbm0p 12 d-a (v out ) ? 78 5 idle channel noise, c-message weighted (-law) ax = 0 db ar = 0 db a-d (pcm output), gx = +8 db +16 dbrnc0 d-a (2 wire), gr = ? 8 db +12 6 coder offset decision value, xn a-d, input signal = 0 v, a-law ? 5+5bits6 7 gx step size 0 gx < 10 db 10 gx 12 db 0.1 0.3 db 4 8 gr step size ? 12 gr 0 db 0.1 9 psrr (v cc ) image frequency input: 4800 to 7800 hz 200 mv p-p measure 8000 hz input frequency a-d 37 db 4 d-a 37 10 group delay pclk 1.53 mhz pclk 1.03 mhz 1014 hz; ? 10 dbm0 b, x, r, and z filters set to default 590 655 s4, 14
aslic/aslac products 23 notes: 1. unless otherwise specified, test conditions are: v cc = 5 v, r tmg = 1200 ? , q bat = bat = ? 51 v, r ab = 35.7 k ? , r bat1 = r bat2 = 365 k ? , r ref = 7.87 k ? , r rx = 75 k ? , r l = 600 ? , r sa = r sb = 200 k ? , c hp = 220 nf, c dc1 = 1.0 f, 5 0 ? fuse resistors, r sr1 = r sr2 = 750 k ? , c ad = c bd = 22 nf, c b = 100 nf and the following network is connected between v tx and r sn : no. item condition min typ max unit note 11 switchhook thresholds all tsh settings ? 0.45 or ? 10 +0.45 or +10 ma % 9, 16, 19 switchhook hysteresis all tsh settings ? 10 % 4 12 ground-key thresholds all tgk settings ? 0.90 or ? 10 +0.90 or +10 ma % 9, 16, 19 ground-key hysteresis all tgk settings ? 10 % 4 13 voltage that sets thermal shutdown bit voltage on aslic device vdc with rab = 35.7 k ? +4.19 v 14 idif fault-current thresholds tip-to-battery fault current (ma) ft, pkft 19.3, 50.6 ? 10 +10 % 16, 19 ft, pkft hysteresis ? 10 4 15 aisn gain accuracy g aisn = 0.0625 ? 16 +16 g aisn = 0.125 ? 8+8 g aisn = 0.1875 ? 6+6 g aisn = ? 0.25 or g aisn +0.25 ? 4+4 16 metering voltage (mtra) accuracy measured at aslac device vm pin ? 7+7 17 metering voltage noise wide-band signal to noise 40 db 18 ring-trip accuracy ? 55%4, 17, 20 19 ring-trip hysteresis v zx i zx 4 5 v a 4, 17 20 power-cross accuracy during transmission ? 10 +10 %17, 20 during ringing ? 10 +10 table 6. aslac device transmission and signaling specifications (continued) rt1 18.75 k rt2 18.75 k ct 430 pf vtx rsn
24 am79213/AM79C203/031 data sheet ambient temperature = 70 c active state, normal polarity for transmission performance 0 dbm = 1 mw @ 600 ? (0.775 vrms) programmed dc feed conditions: vapp (apparent battery voltage) = 50.2 v ila (active state loop-current limit) = 47.6 ma ild (disable state loop-current limit) = 21.2 ma rfd (dc feed resistance) = 403 ? vas (anti-sat activate voltage) = 10.3 v n2 (anti-sat feed resistance factor) = 2 voff (longitudinal offset voltage) = 8.4 v rg = gx = gr = ax = ar = 0 db r, x, b, and z filters set to default aisn = 0 tsh < ild tsh = programmed switchhook detect threshold current ild = programmed disable limit current dc feed conditions are normally set by the aslac device. when the aslic device is tested by itself, its operating conditions must be simulated as if it were connected to an ideal aslac device. when the aslac device is tested by itself, its operating conditions must simulate as if it were connected to an ideal aslic device. 2. these tests are performed with the following load impedances: frequency < 12 khz - longitudinal impedance = 500 ? ; metallic impedance = 300 ? frequency > 12 khz - longitudinal impedance = 90 ? ; metallic impedance = 135 ? 3. this parameter is tested at 1 khz in production. performance at other frequencies is guaranteed by characterization. 4. not tested or partially tested in production. this parameter is guaranteed by characterization or correlation to other tests. 5. when the aslic/aslac devices are in the anti-sat operating region, this parameter will be degraded. the exact degradation will depend on system design. 6. guaranteed by design. 7. overall 1.014 khz insertion loss error of the aslic/aslac devices kit is guaranteed to be 0.34 db. 8. these vbat/qbat, psrr specifications are valid only when the aslic device is used with the aslac device that generates the anti-sat reference. since the anti-sat reference depends upon the battery voltage sensed by the ibat pin of the aslac device, the psrr of the kit will depend upon the amount of battery filtering provided by cb. 9. must meet at least one of these specifications. 10. these voltages are referred to vref. 11. these limits refer to the two-wire output of an ideal aslic device but reflect only the capabilities of the aslac device. 12. when relative levels (dbm0) are used, the specification holds for any setting of (ax + gx) gain from 0 to 12 db or (ar + gr + rg) from 0 to ? 12 db. 13. this parameter tested by inclusion in another test. 14. the group delay specification is defined as the sum of the minimum values of the group delays for the transmit and the recei ve paths when the transmit and receive time slots are identical and the b, x, r, and z filters are disabled with null coefficients . for pclk frequencies between 1.03 mhz and 1.53 mhz, the group delay may vary from one cycle to the next. see also figure 2, group delay distortion. 15. i/o 1 and i/o 2 have an additional circuit that pulls the pin high during 3-state. 16. these limits reflect only the capabilities of the aslac device. 17. rsr1 = rsr2 = 750 k ? , rgfd1 = 510 ? . 18. dc feed performance derates by 5% when operating from ? 40 c to 0 c and 70 c to 85 c. 19. threshold values derate by 5% when operating from ? 40 c to 0 c and 70 c to 85 c. 20. power cross and ring trip values derate by 5% when operating from ? 40 c to 0 c and 70 c to 85 c.
aslic/aslac products 25 in the following section, the transmit path is defined as the section between the analog input to the aslac device (vin) and the pcm voice output of the aslac device a-law/-law speech compressor (shown in the technical overview document). the receive path is defined as the section between the pcm voice input to the aslac device speech expander and the analog output of the aslac device (vout). all limits defined in this section are tested with b = 0, z = 0 and x = r = rg = 1. when rg is enabled, a nominal gain of ? 6.02 db is added to the digital section of the receive path. when ar is enabled, a nominal gain of ? 6.02 db is added to the analog section of the receive path. when ax is enabled, a nominal gain of +6.02 db is added to the analog section of the transmit path. when the gains in the transmit path are set to ax = 0 db and gx = 0 db, a 1014 hz sine wave with a nominal voltage of 0.596 vrms for -law and 0.6 vrms for a-law at the aslac device analog input will correspond to a level of 0 dbm0 at the pcm voice output. under these conditions, the overload level of the transmit path is 1.25 vpeak referenced to vref. when the gains in the receive path are set to ar = gr = 0 db, a 1014 hz sine wave with a level of 0 dbm0 at the pcm voice input will correspond to a nominal voltage of 0.596 vrms for -law and 0.6 vrms for a-law at the analog output of the aslac device. under these conditions, the maximum receive output level is 1.25 vpeak referenced to vref. when relative levels (dbm0) are used in any of the following transmission characteristics, the specification holds for any setting of (ax + gx) gain from 0 to 12 db or (ar + gr + rg) from 0 to ? 12 db. these transmission characteristics are valid for 0 c to 70 c and for vcc = +5 v 0.25 v.
26 am79213/AM79C203/031 data sheet attenuation distortion the deviations from nominal attenuation will stay within the limits shown in figure 1. the reference frequency is 1014 hz and the signal level is ? 10 dbm0. minimum transmit attenuation at 60 hz is 24 db. 3000 3400 2 0.6 0 aslac device specification 0.65 ? 0.125 0.125 600 300 200 0 3200 0.80 0.2 attenuation (db) receive path 1 frequency (hz) figure 1. transmit and receive path attenuation vs. frequency
aslic/aslac products 27 group delay distortion for either transmission path, the group delay distortion is within the limits shown in figure 2. the minimum value of the group delay is taken as the reference. the signal level should be ? 10 dbm0. single frequency distortion the output signal level at any single frequency in the range of 300 hz to 3400 hz, other than that due to an applied 0 dbm0 sine wave signal with frequency f 0 in the same frequency range, is less than ? 46 dbm0. with f 0 swept between 0 to 300 hz and 3400 hz to 12 khz, any generated output signals other than f 0 are less than ? 28 dbm0. this specification is valid for either transmission path. intermodulation distortion two sine wave signals of different frequencies f1 and f2 (not harmonically related) in the range 300 hz to 3400 hz and of equal levels in the range ? 4 dbm0 to ? 21 dbm0 will not produce 2 ? ( f1 ? f2) products having a level greater than ? 42 db relative to the level of the two input signals. a sine wave signal in the frequency band 300 hz to 3400 hz with input level ? 9 dbm0 and a 50 hz signal with input level ? 23 dbm0 will not produce intermodulation products exceeding a level of ? 56 dbm0. these specifications are valid for either transmission path. 0 500 600 1000 2600 2800 90 150 420 delay (s) aslac device specification (either path) frequency (hz) figure 2. group delay distortion
28 am79213/AM79C203/031 data sheet gain linearity the gain deviation relative to the gain at ? 10 dbm0 is within the limits shown in figure 3 (a-law) and figure 4 (- law) for either transmission path when the input is a sine wave signal of 1014 hz. 0.55 0.25 0 ? 0.25 ? 0.55 ? 1.5 ? 55 ? 50 ? 40 ? 10 +3 1.5 gain (db) input level (dbm0) 0 aslac device specification figure 3. a-law gain linearity with tone input (both paths) note: relax specification by 0.05 db at ? 40 c. 0.45 0.25 0 ? 0.25 ? 0.45 ? 1.4 ? 55 ? 50 ? 37 ? 10 +3 1.4 gain (db) input level (dbm0) 0 aslac device specification figure 4. -law gain linearity with tone input (both paths) note: relax specification by 0.05 db at ? 40 c.
aslic/aslac products 29 total distortion, including quantizing distortion the signal-to-total distortion ratio will exceed the limits shown in figure 5 for either path when the input signal is a sine wave signal of frequency 1014 hz. improved distortion at lower levels in lssgr applications can be obtained by proper selection of the gx and gr ranges. figure 5. total distortion with tone input (both paths) input level (dbm0) signal-to-total distortion (db) aslac device specification 0 ? 30 ? 40 ? 45 c d a a-law -law a 35.5 db 35.5 db b 35.5 db 35.5 db c 30 db 31 db d 25 db 27 db b
30 am79213/AM79C203/031 data sheet overload compression figure 6 shows the acceptable region of operation for input signal levels above the reference input power (0 dbm0). the conditions for this figure are: (1) 1 db < transmit path +12 db; (2) ? 12 db receive path < ? 1 db; (3) digital voice output connected to digital voice input; and (4) measurement analog-to-analog. fundamental output power (dbm0) fundamental input power (dbm0) 1 2 3 4 5 6 7 8 9 1234 567 89 acceptable region 2.6 figure 6. a/a overload compression
aslic/aslac products 31 switching characteristics microprocessor interface min. and max. values are valid for all digital outputs with a 100 pf load, except di/o, dxa, and dxb, which are valid with 150 pf loads. table 7. microprocessor interface no. symbol parameter min typ max units note 1t dcy data clock period 244 ns 2t dch data clock high pulse width 97 ns 1 3t dcl data clock low pulse width 97 ns 1 4t dcr rise time of clock 25 ns 5t dcf fall time of clock 25 ns 6t icss chip select setup time, input mode 70 t dcy ? 10 ns 7t icsh chip select hold time, input mode 0 t dch ? 20 ns 8t icsl chip select pulse width, input mode 8t dcy ns 9t icso chip select off time, input mode 5 s 1, 7 10 t ids input data setup time 30 ns 6 11 t idh input data hold time 30 ns 12 t olh slic output latch valid 0 1.2 1.9 s 13 t ocss chip select setup time, output mode 70 t dcy ? 10 ns 14 t ocsh chip select hold time, output mode 0 t dch ? 20 ns 15 t ocsl chip select pulse width, output mode 8t dcy ns 16 t ocso chip select off time, output mode 5 s 1, 7 17 t odd output data turn on delay 50 ns 18 t odh output data hold time 3 ns 19 t odof output data turn off delay 50 ns 20 t odc output data valid 0 50 ns 21 t rst reset pulse width 50 s
32 am79213/AM79C203/031 data sheet table 8. pcm interface no. symbol parameter min typ max units note 22 t pcy pcm clock period 0.122 7.8125 s 2 23 t pch pcm clock high pulse width 48 ns 24 t pcl pcm clock low pulse width 48 ns 25 t pcf fall time of clock 15 ns 26 t pcr rise time of clock 15 ns 27 t fss fs setup time 30 t pcy ? 35 ns 28 t fsh fs hold time 0 ns 29 t fch fs high pulse width t pcy ns 30 t tsd delay to tsc valid 5 80 ns 3 31 t tso delay to tsc off 5 80 ns 3, 4 32 t dxd pcm data output delay 5 80 ns 5 33 t dxh pcm data output hold time 5 80 ns 5 34 t dxz pcm data output delay to high-z 5 80 ns 5 35 t drs pcm data input setup time 25 ns 36 t drh pcm data input hold time 5 ns
aslic/aslac products 33 master clock for 2.048 mhz 100 ppm, 4.096 mhz 100 ppm, or 8.192 mhz 100 ppm operation: notes: 1. dclk may be stopped in the high or low state indefinitely without loss of information. 2. the pcm clock (pclk) frequency must be an integer multiple of the frame sync (fs) frequency with an accuracy of 800 ppm relative to the mclk frequency. this allowance includes any jitter that may occur between the pcm signals (fs, pclk) and mclk. the actual pclk rate is dependent on the number of channels allocated within a frame. the aslac device supports 2 to128 channels. the minimum clock frequency is 128 khz. a pclk of 1.544 mhz may be used for standard u.s. transmission systems. 3. tsc is delayed from fs by a typical value of n ? tpcy, where n is the value stored in the time/clock slot register. 4. t tso is defined as the time at which the output driver turns off. the actual delay time is dependent on the load circuitry. the maximum load capacitance on tsc is 150 pf and the minimum pullup resistance is 360 ? . 5. there is special circuitry that will prevent high-power dissipation from occurring when the dxa or dxb pins of two aslac devices are tied together and one aslac device starts to transmit before the other has gone into a high-impedance state. 6. the first data bit is enabled on the falling edge of chip select or on the falling edge of dclk, whichever occurs last. if ch ip select is held low for less than eight clocks, no command or data is accepted. if chip select is held low for more than eight clocks, the last 8 data bits are used as command or data. 7. the aslac device requires 40 cycles of the 8 mhz internal clock (5 s) between sio operations. if the mpi is being accessed while the mclk (or pclk if in combined clock mode) input is not active, a chip select off time of 20 s is required. table 9. master clock no. symbol parameter min. typ. max. units note 37 t mcy master clock period (2.048 mhz) 488.23 488.28 488.33 ns 2 master clock period (4.096 mhz) 244.11 244.14 244.17 ns master clock period (8.192 mhz) 122.05 122.07 122.09 ns 38 t mcr rise time of clock 15 ns 39 t mcf fall time of clock 15 ns 40 t mch mclk high pulse width 48 ns 41 t mcl mclk low pulse width 48 ns
34 am79213/AM79C203/031 data sheet switching waveforms input and output waveforms for ac tests master clock timing test points 2.0 0.8 2.0 0.8 }{ 2.4 0.45 41 39 v ih v il 37 38 40
aslic/aslac products 35 microprocessor interface (input mode) microprocessor interface (output mode) data valid data valid in/outputs data valid data valid 1 5 vih vil vil vih dclk 9 4 cs data valid 11 12 d in 2 3 8 10 c1, c2, i/o1, i/o2, i/o3*, i/o4* * available on 44-pin version only 7 6 vil vih 16 15 dclk cs data valid data valid d out three-state ol v v oh data valid three-state 13 14 19 20 18 17
36 am79213/AM79C203/031 data sheet pcm highway timing for xe = 0 (transmit on negative pclk edge) time slot zero clock slot zero first bit pclk fs dxa/dxb first bit second bit v ol v oh tsca / tscb v ih v il v ih v il see note 4 27 25 26 23 24 28 35 36 33 34 32 30 31 dra/drb 29 22
aslic/aslac products 37 pcm highway timing for xe = 1 (transmit on positive pclk edge) time slot zero clock slot zero pclk fs first bit second bit v ih v il v ih v il 27 22 25 26 23 24 28 35 36 dra/drb first bit dxa/dxb v ol v oh tsca/ tscb see note 4 33 34 32 30 31 29
38 am79213/AM79C203/031 data sheet table 10. user-programmable components z t is connected between the vtx and rsn pins. the fuse re- sistors are r f . z 2win is the desired 2-wire ac input imped- ance. when computing z t , the internal current amplifier pole and any external stray capacitance between vtx and rsn must be taken into account . z rx is connected from vrx to rsn. z t is defined above, and g 42l is the desired receive gain. thermal management equations (normal active and tip open states) r tmg is connected from tmg to vbat and is used to reduce power dissipation within the aslic device in normal active and tip open states. power dissipated in the thermal management resistor, r tmg , during normal active and tip open states power dissipated in the aslic device while in normal active and tip open states thermal management equations (polarity reverse state) note: aslic device die temperature should not exceed 140 c. power dissipated in the aslic device while in the polarity reverse state total die temperature thermal impedance of the 32-pin plastic leaded chip carrier package z t 63.5 z 2win 2r f ? () ? = z rx z l g 42l ----------- - 254 z t ? z t 63.5 z l 2r f + () ? + --------------------------------------------------------- ? = r tmg v bat voff ? i loop ------------------------------------ - = p rtmg v bat voff ? i loop r l ? () ? () 2 r tmg ----------------------------------------------------------------------------------- = p slic v bat i loop ? p rtmg ? r l i loop () ? 2 ? 0.12 w + = p slic v bat i loop r l i loop () 2 ? () ? ? 0.12 w + = t slic p slic ja t ambient + ? = thetaja ja () 43 ? watt =
aslic/aslac products 39 aslic/aslac devices linecard schematic ad rsn vtx hpa hpb chp sa isum idif c1 c2 ring bus rrx c.o. battery vref vref vout vin isum idif iab ringout iref rref c1 c2 i/o1 i/o2 ry1out k1 agnd dgnd vcca vccd vcc gnd bgnd +5 v c3 cbat ry2out tmg rtmg a rfa cad rfb bd sb bal1 vcc u3 c4 k1a k2 k1b b k2b k2a rsa rsb vdc k3 rgfd1 +5 v +5 v 1 2 3 4 rsr2 rsr1 vlbias vlbias c.o. battery c5 irta irtb idc idc d1 ry3out k4 rm vm cdc1 rt ibat qbat + rbat1 cb rbat2 + + + + cs + + polarized capacitor non polarized capacitor + indicates bias battery ground analog ground digital ground dra dxa mpi & pcm highway dual pcm highway (32-/44-pin plcc) *these pins are unavailable for 32-pin plcc option. *i/o3 *i/o4 cm vref cdif vbat rsvd *dxb *drb fs rst pclk mclk di/o dclk cs tsca *tscb int ( ? ) cbd test bus r t e s t rab aslic (32-pin plcc) aslic (32-/44-pin plcc) u1 u2 figure 7. aslic/aslac typical linecard schematic nc notes: 1. this application ckt is valid only to 2.2 v metering. 2. if the rsb sense resistor is moved so that it is exposed to the ringing voltage, see the discussion in the line fault alarm section.
40 am79213/AM79C203/031 data sheet note: * value can be adjusted to suit application. table 11. aslic/aslac devices linecard parts list item type value tol. rating comments u1 aslic device u2 aslac device u3 tcm1060 transient voltage suppressor, texas instruments d1 diode 100 ma 100 v 1n4002 rfa, rfb resistor 50 ? 2% 2 w fusible protection resistors rsa, rsb resistor 200 k ? 2% 1/4 w sense resistors rsr1, rsr2 resistor 750 k ? 2% 1/4 w matched to within 0.2% for initial tolerance and 0 to 70 c ambient temperature range. 17 mw typ rgfd1 resistor 510 ? 2% 2 w 1.2 w typ rrx* resistor 51.1 k ? 1% 1/8 w <1 mw rt* resistor 51.1 k ? 1% 1/8 w <1mw rbat1, rbat2 resistor 365 k ? 1% 1/8 w <5 mw rab resistor 35.7 k ? 1% 1/8 w <1 mw rref resistor 7.87 k ? 1% 1/8 w <1 mw rtmg * resistor 1600 ? 5% 4 w application dependent rm* resistor 3.16 k ? 1% 1/8 w application dependent rtest resistor 3 k ? 1% 5 w used only if ringing tests are required. cdif capacitor 6.8 nf 20% 5 v ceramic cad, cbd * capacitor 22 nf 10% 100 v ceramic, not voltage sensitive cbat capacitor 150 nf 20% 100 v ceramic, vbat typ. chp capacitor 220 nf 20% 100 v ceramic, vbat typ. cb capacitor 100 nf 20% 100 v ceramic, 0.5 vbat typ cdc1 capacitor 1.0 f 20% 5 v ceramic cm* capacitor 1.8 nf 10% 5 v ceramic cs * capacitor 100 nf 20% 100 v protector speed up capacitor k1 relay 5 v coil 200 mw dpdt ring relay k2 relay 5 v coil 200 mw dpdt (optional) line circuit test k3, k4 relay 5 v coil 200 mw optional
aslic/aslac products 41 programmable filters general description of csd coefficients the filter functions are performed by a series of multiplications and accumulations. a multiplication is accomplished by repeatedly shifting the multiplicand and summing the result with the previous value at that summation node. the method used in the aslac device is known as canonic signed digit (csd) multiplication and splits each coefficient into a series of csd coefficients. each programmable fir filter section has the following general transfer function: equation (1) where the number of taps in the filter = n + 1. the transfer function for iir part of z and b filters is: equation (2) the values of the user-defined coefficients (h i ) are assigned via the mpi. each of the coefficients (h i ) is defined in the following general equation: equation (3) where: m i = the number of shifts = m i m i + 1 b i = sign = 1 n = number of csd coefficients. the value of h i in equation 3 represents a decimal number which is broken down into a sum of successive values of: 1.0 multiplied by 2 ? 0 , or 2 ? 1 , or 2 ? 2 ? 2 ? 7 ? or 1.0 multiplied by 1, or 1/2, or 1/4 ? 1/128 ? the limit on the negative powers of 2 is determined by the length of the registers in the alu. the coefficient h i in equation 3 can be considered to be a value made up of n binary 1s in a binary register where the left part represents whole numbers, the right part represents decimal fractions, and a decimal point separates them. the first binary 1 is shifted m 1 bits to the right of the decimal point; the second binary 1 is shifted m 2 bits to the right of the decimal point; the third binary 1 is shifted m 3 bits to the right of the decimal point, and so on. note that when m 1 is 0, the resulting value is a binary 1 in front of the decimal point, that is, no shift. if m 2 is also 0, the result is another binary 1 in front of the decimal point, giving a total value of binary 10 in front of the decimal point (i.e., a decimal value of 2.0). the value of n, therefore, determines the range of values the coefficient h i can take (e.g., if n = 3 the maximum and minimum values are 3, and if n = 4 the values are between 4). detailed description of aslac device coefficients the csd coding scheme in the aslac device uses a value called m i , where m i represents the distance shifted right of the decimal point for the first binary 1. m 2 represents the distance shifted to the right of the previous binary 1, and m 3 represents the number of shifts to the right of the second binary 1. note that the range of values determined by n is unchanged. equation 3 is now modified (in the case of n = 4) to: equation (4) equation (5) equation (6) hf z () h 0 h 1 z 1 ? h 2 z 2 ? h n z n ? ++++ = hl z () 1 1h n1 + () z 1 ? ? --------------------------------- = h i b 1 2 m 1 ? b 2 2 m 2 ? b n 2 m n ? ++++ = h i b 1 2 m 1 ? b 2 2 m 2 ? b 3 2 m 3 ? b 4 2 m 4 ? +++ = h i c 1 2 m 1 ? c 1 c 2 2 m 1 m 2 + () ? c 1 c 2 c 3 2 m 1 m 2 m 3 ++ () ? c 1 c 2 c 3 c 4 2 m 1 m 2 m 3 m 4 +++ () ? ++ + = h i c 1 2 m 1 ? 1c 2 2 m 2 ? 1c 3 2 m 3 ? 1c 4 2 m 4 ? + () + [] + =
42 am79213/AM79C203/031 data sheet where: m 1 = m 1 b 1 = c 1 m 2 = m 1 +m 2 b 2 = c 1 ? c 2 m 3 = m 1 +m 2 +m 3 b 3 = c 1 ? c 2 ? c 3 m 4 = m 1 +m 2 +m 3 +m 4 b 4 = c 1 ? c 2 ? c 3 ? c 4 in the aslac device, a coefficient, h i , consists of n csd coefficients, each being made up of 4 bits and formatted as c xy m xy , where c xy is one bit (msb) and m xy is 3 bits. each csd coefficient is broken down as follows: c xy is the sign bit (0 = positive, 1 = negative). m xy is the 3-bit shift code. it is encoded as a binary number as follows: 000: 0 shifts 001: 1 shifts 010: 2 shifts 011: 3 shifts 100: 4 shifts 101: 5 shifts 110: 6 shifts 111: 7 shifts y is the coefficient number (the i in h i ). x is the position of this csd coefficient within the h i coefficient. the most significant binary 1 is represented by x = 1. the next most significant binary 1 is represented by x = 2, and so on. thus, c 13 m 13 represents the sign and the relative shift position for the first (most significant) binary 1 in the 4th (h 3 ) coefficient. the number of csd coefficients, n, is limited to 4 in the gr, gx, r, x, z, and the iir part of the b filter, and 3 for the fir part of the b filter. note also that the gx-filter coefficient equation is slightly different from the other filters. equation (7) please refer to the am79213/AM79C203/031 technical reference, pid 21325a detailing the commands for complete details on programming the coefficients. h igx 1h i + =
aslic/aslac products 43 physical dimension pl032 pl044 .050 ref. .026 .032 top view pin 1 i.d. .485 .495 .447 .453 .585 .595 .547 .553 16-038fpo-5 pl 032 da79 6-28-94 ae side view seating plane .125 .140 .009 .015 .080 .095 .042 .056 .013 .021 .400 ref. .490 .530 top view seating plane .685 .695 .650 .656 pin 1 i.d. .685 .695 .650 .656 .026 .032 .050 ref .042 .056 .062 .083 .013 .021 .590 .630 .500 ref .009 .015 .165 .180 .090 .120 16-038-sq pl 044 da78 6-28-94 ae side view
44 am79213/AM79C203/031 data sheet revision summary revision a to revision b ? fixed the figure numbering. ? minor changes were made to the data sheet style and format to conform to legerity standards. revision b to revision c ? the physical dimension (pl032 and pl044) was added to the physical dimension section. ? updated the pin description table to correct inconsistencies. ? minor changes were made to the data sheet style and format to conform to legerity standards. revision c to revision d ? page 26, attenuation distortion, the sentence ?the attenuation of the signal in either path is nominally inde- pendent of the frequency? was deleted.
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